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ltc2379-18 1 237918f typical application features description 18-bit, 1.6msps, low power sar adc with 101.2db snr the ltc ? 2379-18 is a low noise, low power, high speed 18-bit successive approximation register (sar) adc. op - erating from a 2.5v supply, the ltc2379-18 has a v ref fully differential input range with v ref ranging from 2.5v to 5.1v. the ltc2379-18 consumes only 18mw and achieves 2lsb inl maximum, no missing codes at 18-bits with 101.2db snr. the ltc2379-18 has a high speed spi-compatible se - rial interface that supports 1.8v, 2.5v, 3.3v and 5v logic while also featuring a daisychain mode. the fast 1.6msps throughput with no cycle latency makes the ltc2379-18 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing exter - nal timing considerations. the ltc2379-18 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate. the ltc2379-18 features a unique digital gain compres - sion (dgc) function, which eliminates the driver amplifiers negative supply while preserving the full resolution of the adc. when enabled, the adc performs a digital scaling function that maps zero-scale code from 0v to 0.1 ? v ref and full-scale code from v ref to 0.9 ? v ref . for a typical reference voltage of 5v, the full-scale input range is now 0.5v to 4.5v, which provides adequate headroom for powering the driving amplifier from a single 5.5v supply. 32k point fft f s = 1.6msps, f in = 2khz applications n 1.6msps throughput rate n 2lsb inl (max) n guaranteed 18-bit no missing codes n low power: 18mw at 1.6msps, 18w at 1.6ksps n 101.2db snr (typ) at f in = 2khz n C 120db thd (typ) at f in = 2khz n digital gain compression (dgc) n guaranteed operation to 125c n 2.5v supply n fully differential input range v ref n v ref input range from 2.5v to 5.1v n no pipeline delay, no cycle latency n 1.8v to 5v i/o voltages n spi-compatible serial i/o with daisychain mode n internal conversion clock n 16-pin msop and 4mm 3mm dfn packages n medical imaging n high speed data acquisition n portable or compact instrumentation n industrial process control n low power battery-operated instrumentation n ate frequency (khz) 0 100 200 300 400 800 700 600 500 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237918 ta02 snr = 101.2db thd = ?120db sinad = 101.1db sfdr = 121db 20 v ref 0v v ref 0v 20 3300pf 3300pf 3300pf ? + v ref sample clock 237918 ta01 10f 0.1f 2.5v ref 1.8v to 5v 2.5v to 5.1v 47f (x5r, 0805 size) ref gnd chain rdl/sdi sdo sck busy cnv ref/dgc ltc2379-18 v dd ov dd in + in ? l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2379-18 2 237918f pin configuration absolute maximum ratings supply voltage (v dd ) ............................................... 2.8v supply voltage (ov dd ) ................................................ 6v reference input (ref) ................................................. 6v analog input voltage (note 3) in + , in C ......................... (gnd C0.3v) to (ref + 0.3v) ref/ dgc input (note 3) .... (gnd C0.3v) to (ref + 0.3v) digital input voltage (note 3) ........................... (gnd C0.3v) to (ov dd + 0.3v) (notes 1, 2) 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 gnd ov dd sdo sck rdl/sdi busy gnd cnv chain v dd gnd in + in ? gnd ref ref/dgc top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w exposed pad (pin 17) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 chain v dd gnd in + in ? gnd ref ref/dgc 16 15 14 13 12 11 10 9 gnd ov dd sdo sck rdl/sdi busy gnd cnv top view ms package 16-lead plastic msop t jmax = 150c, ja = 110c/w order information lead free finish tape and reel part marking* package description temperature range ltc2379cms-18#pbf ltc2379cms-18#trpbf 237918 16-lead plastic msop 0c to 70c ltc2379ims-18#pbf ltc2379ims-18#trpbf 237918 16-lead plastic msop C40c to 85c ltc2379hms-18#pbf ltc2379hms-18#trpbf 237918 16-lead plastic msop C40c to 125c ltc2379cde-18#pbf ltc2379cde-18#trpbf 23798 16-lead (4mm 3mm) plastic dfn 0c to 70c ltc2379ide-18#pbf ltc2379ide-18#trpbf 23798 16-lead (4mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ digital output voltage (note 3) ........................... (gnd C0.3v) to (ov dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc2379c ................................................ 0c to 70c ltc2379i ............................................. C40c to 85c ltc2379h .......................................... C40c to 125c storage temperature range .................. C65c to 150c
ltc2379-18 3 237918f dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 2khz, v ref = 5v l 97.8 101 db f in = 2khz, v ref = 5v, (h-grade) l 97.3 101 db snr signal-to-noise ratio f in = 2khz, v ref = 5v f in = 2khz, v ref = 5v, ref/ dgc = gnd f in = 2khz, v ref = 2.5v l l l 98.1 96.3 92.3 101.2 99 96 db db db f in = 2khz, v ref = 5v, (h-grade) f in = 2khz, v ref = 5v, ref/ dgc = gnd, (h-grade) f in = 2khz, v ref = 2.5v, (h-grade) l l l 97.7 95.8 92 101.2 99 96 db db db thd total harmonic distortion f in = 2khz, v ref = 5v f in = 2khz, v ref = 5v, ref/ dgc = gnd f in = 2khz, v ref = 2.5v l l l C108.6 C104.7 C99.6 C120 C119 C107 db db db f in = 2khz, v ref = 5v, (h-grade) f in = 2khz, v ref = 5v, ref/ dgc = gnd, (h-grade) f in = 2khz, v ref = 2.5v, (h-grade) l l l C108.1 C102.8 C99.4 C120 C119 C107 db db db sfdr spurious free dynamic range f in = 2khz, v ref = 5v 122 db C3db input bandwidth 34 mhz aperture delay 500 ps aperture jitter 4 ps transient response full-scale step 200 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 8) electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C0.05 v ref + 0.05 v v in C absolute input range (in C ) (note 5) l C0.05 v ref + 0.05 v v in + C v in C input differential voltage range v in = v in + C v in C l Cv ref +v ref v v cm common-mode input range l v ref /2C 0.05 v ref /2 v ref /2+ 0.05 v i in analog input leakage current l 1 a c in analog input capacitance sample mode hold mode 45 5 pf pf cmrr input common mode rejection ratio f in = 800khz 86 db the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) converter characteristics symbol parameter conditions min typ max units resolution l 18 bits no missing codes l 18 bits transition noise 0.8 lsb rms inl integral linearity error (note 6) l C2 0.8 2 lsb dnl differential linearity error l C0.9 0.2 0.9 lsb bze bipolar zero-scale error (note 7) l C9 0 9 lsb bipolar zero-scale error drift 3 mlsb/c fse bipolar full-scale error (note 7) l C40 7 40 lsb bipolar full-scale error drift 0.05 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4)
ltc2379-18 4 237918f adc timing characteristics symbol parameter conditions min typ max units f smpl maximum sampling frequency l 1.6 msps t conv conversion time l 360 412 ns t acq acquisition time t acq = t cyc Ct conv C t busylh (note 10) l 200 ns t cyc time between conversions l 625 ns t cnvh cnv high time l 20 ns t busylh cnv to busy delay c l = 20pf l 13 ns t cnvl minimum low time for cnv (note 11) l 20 ns t quiet sck quiet time from cnv (note 10) l 20 ns t sck sck period (notes 11, 12) l 10 ns t sckh sck high time l 4 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) power requirements symbol parameter conditions min typ max units v dd supply voltage l 2.375 2.5 2.625 v ov dd supply voltage l 1.71 5.25 v i vdd i ovdd i pd i pd supply current supply current power down mode power down mode 1.6msps sample rate 1.6msps sample rate (c l = 20pf) conversion done (i vdd + i ovdd + i ref ) conversion done (i vdd + i ovdd + i ref , h-grade) l l l 7.2 1.1 0.9 0.9 8.6 90 140 ma ma a a p d power dissipation power down mode power down mode 1.6msps sample rate conversion done (i vdd + i ovdd + i ref ) conversion done (i vdd + i ovdd + i ref , h-grade) 18 2.25 2.25 21.5 225 315 mw w w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) reference input symbol parameter conditions min typ max units v ref reference voltage (note 5) l 2.5 5.1 v i ref reference input current (note 9) l 1 1.3 ma v ih dgc high level input voltage ref/ dgc pin l 0.8v ref v v il dgc low level input voltage ref/ dgc pin l 0.2v ref v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500 a l ov dd C 0.2 v v ol low level output voltage i o = 500 a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4)
ltc2379-18 5 237918f adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 11) l 4 ns t hsdisck sdi hold time from sck (note 11) l 1 ns t sckch sck period in chain mode t sckch = t ssdisck + t dsdo (note 11) l 13.5 ns t dsdo sdo data valid delay from sck c l = 20pf (note 11) l 9.5 ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 10) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 10) l 5 ns t en bus enable time after rdl (note 11) l 16 ns t dis bus relinquish time after rdl (note 11) l 13 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may effect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above ref or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above ref or ov dd without latch-up. note 4: v dd = 2.5v, ov dd = 2.5v, ref = 5v, f smpl = 1.6mhz, ref/ dgc = v ref . note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 5v input with a 5v reference voltage. note 9: f smpl = 1.6mhz, i ref varies proportionately with sample rate. note 10: guaranteed by design, not subject to test. note 11: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 12: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising capture. 0.8*ov dd 0.2*ov dd 50% 50% 237918 f01 0.2*ov dd 0.8*ov dd 0.2*ov dd 0.8*ov dd t delay t width t delay figure 1. voltage levels for timing specifications
ltc2379-18 6 237918f typical performance characteristics 32k point fft f s = 1.6msps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs reference voltage, f in = 2khz thd, harmonics vs reference voltage, f in = 2khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram output code 0 65536 131072 196608 262144 ?2.0 inl error (lsb) 0.0 0.5 1.0 1.5 ?0.5 ?1.0 ?1.5 2.0 238018 g01 frequency (khz) 0 100 200 300 400 800 700 600 500 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237918 g04 snr = 101.2db thd = ?120db sinad = 101.1db sfdr = 121db output code ?1.0 dnl error (lsb) 0.8 0.6 0.4 0.2 0.0 ?0.8 ?0.6 ?0.4 ?0.2 1.0 237918 g02 0 65536 131072 196608 262144 code 131073 131072 131071 131070 131069 131068 0 counts 10000 60000 40000 20000 50000 30000 70000 237918 g03 = 0.8 t a = 25c, v dd = 2.5v, ov dd = 2.5v, ref = 5v, f smpl = 1.6msps, unless otherwise noted. input level (db) snr, sinad (dbfs) 102.0 237918 g07 100.0 100.5 101.0 101.5 ?40 ?30 ?20 ?10 0 sinad snr reference voltage (v) snr, sinad (dbfs) 102 237918 g16 95 96 97 98 99 100 101 2.5 3.0 3.5 4.0 4.5 5.0 sinad snr harmonics, thd (dbfs) ?100 ?110 237918 g17 ?140 ?135 ?130 ?125 ?120 ?115 ?105 thd 2nd 3rd reference voltage (v) 2.5 3.0 3.5 4.0 4.5 5.0 frequency (khz) snr, sinad (dbfs) 105 237918 g05 80 85 90 95 100 0 25 50 75 100 125 150 175 200 snr sinad frequency (khz) harmonics, thd (dbfs) ?80 237918 g06 ?140 ?130 ?120 ?110 ?100 ?90 0 25 50 75 100 125 150 175 200 thd 3rd 2nd
ltc2379-18 7 237918f snr, sinad vs temperature, f in = 2khz thd, harmonics vs temperature, f in = 2khz typical performance characteristics supply current vs temperature shutdown current vs temperature cmrr vs input frequency reference current vs reference voltage inl/dnl vs temperature full-scale error vs temperature offset error vs temperature t a = 25c, v dd = 2.5v, ov dd = 2.5v, ref = 5v, f smpl = 1.6msps, unless otherwise noted. frequency (khz) 0 200 400 600 800 70 cmrr (db) 85 80 75 100 95 90 237918 g15 0 reference current (ma) 0.5 0.4 0.2 0.1 0.3 1.0 0.9 0.8 0.7 0.6 237918 g18 reference voltage (v) 2.5 3.0 3.5 4.0 4.5 5.0 temperature (c) snr, sinad (dbfs) 103 102 237918 g08 96 97 98 99 100 101 ?55 ?35 ?15 5 25 45 65 85 105 125 sinad snr temperature ( c) harmonics, thd (dbfs) ?110 237918 g09 ?135 ?130 ?125 ?120 ?115 ?55 ?35 ?15 5 25 45 65 85 105 125 thd 2nd 3rd temperature (c) inl/dnl error (lsb) 2 237918 g10 ?2 ?1 0 1 ?55 ?35 25 45 65 ?15 5 85 105 125 max inl max dnl min dnl min inl temperature (c) full-scale error (lsb) 8 237918 g11 ?8 0 4 2 6 ?4 ?2 ?6 ?55 ?35 25 45 65 ?15 5 85 105 125 ?fs +fs temperature (c) power supply current (ma) 8 7 6 237918 g13 0 1 2 3 4 5 ?55 ?35 ?15 5 25 45 65 85 105 125 i vdd i ref i ovdd temperature (c) offset error (lsb) 2.0 1.5 1.0 0.5 237918 g12 ?2.0 ?1.0 0 ?0.5 ?1.5 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) power-down current (a) 45 40 35 30 237918 g14 0 5 10 15 20 25 ?55 ?35 ?15 5 25 45 65 85 105 125 i vdd + i ovdd + i ref
ltc2379-18 8 237918f chain (pin 1): chain mode selector pin. when low, the ltc2379-18 operates in normal mode and the rdl/sdi input pin functions to enable or disable sdo. when high, the ltc2379-18 operates in chain mode and the rdl/ sdi pin functions as sdi, the daisychain serial data input. logic levels are determined by 0v dd . v dd (pin 2): 2.5v power supply. the range of v dd is 2.375v to 2.625v. bypass v dd to gnd with a 10f ceramic capacitor. gnd (pins 3, 6, 10 and 16): ground. in + , in C (pins 4, 5): positive and negative differential analog inputs. ref (pin 7): reference input. the range of ref is 2.5v to 5.1v. this pin is referred to the gnd pin and should be decoupled closely to the pin with a 47f ceramic capacitor (x5r, 0805 size). ref/ dgc (pin 8): when tied to ref, digital gain compression is disabled and the ltc2379-18 defines full-scale according to the v ref analog input range. when tied to gnd, digital gain compression is enabled and the ltc2379-18 defines full-scale with inputs that swing between 10% and 90% of the v ref analog input range. cnv (pin 9): convert input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by 0v dd . busy (pin 11): busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by 0v dd . rdl/sdi (pin 12): when chain is low, the part is in nor - mal mode and the pin is treated as a bus enabling input. when chain is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another adc in the daisychain is input. logic levels are determined by 0v dd . sck (pin 13): serial data clock input. when sdo is enabled, the conversion result or daisychain data from another adc is shifted out on the rising edges of this clock msb first. logic levels are determined by 0v dd . sdo (pin 14): serial data output. the conversion result or daisychain data is output on this pin on each rising edge of sck msb first. the output data is in 2s complement format. logic levels are determined by 0v dd . ov dd (pin 15): i/o interface digital power. the range of ov dd is 1.71v to 5.25v. this supply is nominally set to the same supply as the host interface (1.8v, 2.5v, 3.3v, or 5v). bypass ov dd to gnd with a 0.1f capacitor. gnd (exposed pad pin 17 C dfn package only): ground. exposed pad must be soldered directly to the ground plane. functional block diagram pin functions ref = 5v ltc2379-18 in + v dd = 2.5v ov dd = 1.8v to 5v in ? chain cnv gnd busy ref/dgc sdo sck rdl/sdi control logic 18-bit sampling adc spi port + ? 237918 bd01
ltc2379-18 9 237918f timing diagram power-down and acquire convert d15 d14 d17 d16 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo sck cnv chain, rdl/sdi = 0 busy 237918 td02 conversion timing using the serial interface
ltc2379-18 10 237918f overview the ltc2379-18 is a low noise, low power, high speed 18-bit successive approximation register (sar) adc. operating from a single 2.5v supply, the ltc2379-18 supports a large and flexible v ref fully differential input range with v ref ranging from 2.5v to 5.1v, making it ideal for high performance applications which require a wide dynamic range. the ltc2379-18 achieves 2lsb inl max, no missing codes at 18-bits and 101.2db snr. fast 1.6msps throughput with no cycle latency makes the ltc2379-18 ideally suited for a wide variety of high speed applications. an internal oscillator sets the con - version time, easing external timing considerations. the ltc2379-18 dissipates only 18mw at 1.6msps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. the ltc2379-18 features a unique digital gain compres - sion (dgc) function, which eliminates the driver amplifiers negative supply while preserving the full resolution of the adc. when enabled, the adc performs a digital scaling function that maps zero-scale code from 0v to 0.1 ? v ref and full-scale code from v ref to 0.9 ? v ref . for a typical reference voltage of 5v, the full-scale input range is now 0.5v to 4.5v, which provides adequate headroom for powering the driving amplifier from a single 5.5v supply. converter operation the ltc2379-18 operates in two phases. during the ac - quisition phase, the charge redistribution capacitor d/a converter (cdac) is connected to the in + and in C pins to sample the differential analog input voltage. a rising edge on the cnv pin initiates a conversion. during the conversion phase, the 18-bit cdac is sequenced through a succes - sive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the refer - ence voltage (e.g. v ref /2, v ref /4 v ref /262144) using the differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 18-bit digital output code for serial transfer. applications information figure 2. ltc2379-18 transfer function input voltage (v) 0v output code (two?s complement) ?1 lsb 237918 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/262144 transfer function the ltc2379-18 digitizes the full-scale voltage of 2 ref into 2 18 levels, resulting in an lsb size of 38v with ref = 5v. the ideal transfer function is shown in figure 2. the output data is in 2s complement format. r on 40 c in 45pf r on 40 ref ref c in 45pf in + in ? bias voltage 237918 f03 figure 3. the equivalent circuit for the differential analog input of the ltc2379-18 analog input the analog inputs of the ltc2379-18 are fully differential in order to maximize the signal swing that can be digitized. the analog inputs can be modeled by the equivalent circuit shown in figure 3. the diodes at the input provide esd protection. in the acquisition phase, each input sees ap - proximately 45pf (c in ) from the sampling cdac in series with 40? (r on ) from the on-resistance of the sampling switch. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the adc. the inputs draw a current spike while charging the c in capacitors during acquisition. during conversion, the analog inputs draw only a small leakage current.
ltc2379-18 11 237918f applications information input drive circuits a low impedance source can directly drive the high im - pedance inputs of the ltc2379-18 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis - tortion performance of the adc. minimizing settling time is important even for dc inputs, because the adc inputs draw a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2379-18. the ampli - fier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the current spike the adc inputs draw. input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise. the simple 1-pole rc lowpass filter (lpf1) shown in figure 4 is sufficient for many applications. 20 3300pf 6600pf 20 500 lpf2 lpf1 bw = 800khz bw = 48khz single-ended- to-differential driver single-ended- input signal ltc2379-18 in + in ? 237918 f04 3300pf 3300pf high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. single-ended-to-differential conversion for single-ended input signals, a single-ended to differential conversion circuit must be used to produce a differential signal at the inputs of the ltc2379-18. the lt6350 adc driver is recommended for performing single-ended-to- differential conversions. the lt6350 is flexible and may be configured to convert single-ended signals of various amplitudes to the 5v differential input range of the ltc2379-18. the lt6350 is also available in h-grade to complement the extended temperature operation of the ltc2379-18 up to 125c. figure 5a shows the lt6350 being used to convert a 0v to 5v single-ended input signal. in this case, the first amplifier is configured as a unity gain buffer and the single- ended input signal directly drives the high-impedance input of the amplifier. as shown in the fft of figure 5b, the lt6350 drives the ltc2379-18 to near full datasheet performance. the lt6350 can also be used to buffer and convert large true bipolar signals which swing below ground to the 5v differential input range of the ltc2379-18 in order to maximize the signal swing that can be digitized. fig - ure?6a shows the lt6350 being used to convert a 10v true bipolar signal for use by the ltc2379-18. in this case, the first amplifier in the lt6350 is configured as an inverting amplifier stage, which acts to attenuate and level shift the input signal to the 0v to 5v input range of the ltc2379-18. in the inverting amplifier configuration, the single-ended input signal source no longer directly drives a high impedance input of the first amplifier. the input impedance is instead set by resistor r in . r in must be chosen carefully based on the source impedance of the signal source. higher values of r in tend to degrade both the noise and distortion of the lt6350 and ltc2379-18 as a system. figure 4. input signal chain another filter network consisting of lpf2 should be used between the buffer and adc input to both minimize the noise contribution of the buffer and to help minimize distur - bances reflected into the buffer from sampling transients. long rc time constants at the analog inputs will slow down the settling of the analog inputs. therefore, lpf2 requires a wider bandwidth than lpf1. a buffer amplifier with a low noise density must be selected to minimize degradation of the snr.
ltc2379-18 12 237918f r1, r2, r3 and r4 must be selected in relation to r in to achieve the desired attenuation and to maintain a balanced input impedance in the first amplifier. table 1 shows the resulting snr and thd for several values of r in , r1, r2, r3 and r4 in this configuration. figure 6b shows the re - sulting fft when using the lt6350 as shown in figure 6a. table 1. snr, thd vs r in for 10v single-ended input signal. r in () r1 () r2 () r3 () r4 () snr (db) thd (db) 2k 499 499 2k 402 100.8 C99 10k 2.49k 2.49k 10k 2k 100.5 C94 100k 24.9k 24.9k 100k 20k 94.8 C96 fully differential inputs to achieve the full distortion performance of the ltc2379 - 18, a low distortion fully differential signal source driven through the lt6203 configured as two unity gain buffers as shown in figure 7 can be used to get the full data sheet thd specification of C120db. applications information lt6350 r1 = 499 r2 = 499 r3 = 2k r4 = 402 v cm = v ref /2 v cm 237918 f06a out1 r int r int r in = 2k out2 8 4 5 2 1 + ? + ? ? + 220pf 10f 200pf 0v 5v ?10v 10v 0v 0v 5v digital gain compression the ltc2379-18 offers a digital gain compression (dgc) feature which defines the full-scale input swing to be be - tween 10% and 90% of the v ref analog input range. to enable digital gain compression, bring the ref/ dgc pin low. this feature allows the lt6350 to be powered off of a single +5.5v supply since each input swings between 0.5v and 4.5v as shown in figure 8. needing only one figure 6a. lt6350 converting a 10v single-ended signal to a 5v differential input signal figure 6b. 32k point fft plot with f in = 2khz for circuit shown in figure 6a figure 7. lt6203 buffering a fully differential signal source ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237918 f06b snr = 100.8db thd = ?99.3db sinad = 97.8db sfdr = 101.2db frequency (khz) 0 100 200 300 400 800 700 600 500 lt6203 237918 f07 0v 5v 0v 5v 3 1 2 + ? 0v 5v 5 7 6 + ? 0v 5v lt6350 v cm = v ref /2 237918 f05a 0v 5v 0v 5v out1 r int r int out2 8 4 5 2 1 + ? + ? ? + 0v 5v frequency (khz) 0 100 200 300 400 800 700 600 500 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237918 f05b snr = 101db thd = ?111.5db sinad = 100.8db sfdr = 114.5db figure 5a. lt6350 converting a 0v-5v single-ended signal to a 5v differential input signal figure 5b. 32k point fft plot with f in = 2khz for circuit shown in figure 5a
ltc2379-18 13 237918f ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237918 f09b snr = 99db thd = ?95db sinad = 94.6db sfdr = 96.3db frequency (khz) 0 100 200 300 400 800 700 600 500 figure 9b. 32k point fft plot with f in = 2khz for circuit shown in figure 9a figure 8. input swing of the ltc2379 with gain compression enabled applications information positive supply to power the lt6350 results in additional power savings for the entire system. figure 9a shows how to configure the lt6350 to accept a 10v true bipolar input signal and attenuate and level shift the signal to the reduced input range of the ltc2379 -18 when digital gain compression is enabled. figure 9b shows an fft plot with the ltc2379-18 being driven by the lt6350 with digital gain compression enabled. adc reference the ltc2379-18 requires an external reference to define its input range. a low noise, low temperature drift refer - ence is critical to achieving the full datasheet performance of the adc. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power and high accuracy, the ltc6655-5 is particularly well suited for use with the ltc2379-18. the ltc6655-5 offers 0.025% (max) initial accuracy and 2ppm/c (max) temperature coefficient for high precision applications. the ltc6655-5 is fully specified over the h-grade temperature range and complements the extended temperature operation of the ltc2379-18 up to 125c. we recommend bypassing the ltc6655-5 with a 47f ceramic capacitor (x5r, 0805 size) close to the ref pin. the ref pin of the ltc2379-18 draws charge (q conv ) from the 47f bypass capacitor during each conversion cycle. the reference replenishes this charge with a dc current, i ref = q conv /t cyc . the dc current draw of the ref pin, i ref , depends on the sampling rate and output code. if the ltc2379-18 is used to continuously sample a signal at a constant rate, the ltc6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5lsbs. when idling, the ref pin on the ltc2379-18 draws only a small leakage current (< 1a). in applications where a burst of samples is taken after idling for long periods as shown in figure 10, i ref quickly goes from approximately cnv idle period idle period 237918 f10 figure 10. cnv waveform showing burst sampling figure 9a. lt6350 configured to accept a 10v input signal while running off of a single 5.5v supply when digital gain compression is enabled in the ltc2379-18 237918 f08 5v 4.5v 0.5v 0v lt6350 3.01k 4.32k v cm 237918 f09a out1 r int r int r in = 15k out2 v ? 8 4 5 2 1 6 v + 3 + ? ? + 20 3300pf 20 6.04k 1k v cm 1k 0.5v 4.5v 0.5v 4.5v 5v 5.5v 47f 10f 10f ltc2379-18 ref/dgc in + ref v dd 2.5v in ? ltc6655-5 v in v out_s v out_f ?10v 10v 0v 3300pf 3300pf
ltc2379-18 14 237918f figure 11. 32k point fft with f in = 2khz of the ltc2379-18 frequency (khz) 0 100 200 300 400 800 700 600 500 ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 237918 f11 snr = 101.2db thd = ?120db sinad = 101.1db sfdr = 121db applications information 0a to a maximum of 1.3ma at 1.6msps. this step in dc current draw triggers a transient response in the reference that must be considered since any deviation in the refer - ence output voltage will affect the accuracy of the output code. in applications where the transient response of the reference is important, the fast settling ltc6655-5 refer - ence is also recommended. dynamic performance fast fourier transform (fft) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the ltc2379-18 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 11 shows that the ltc2379-18 achieves a typical sinad of 101db at a 1.6mhz sampling rate with a 2khz input. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 11 shows that the ltc2379-18 achieves a typical snr of 101.2db at a 1.6mhz sampling rate with a 2khz input. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: th d = 20 l og v 2 2 + v 3 2 + v 4 2 + + v n 2 v 1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through v n are the amplitudes of the second through nth harmonics. power considerations the ltc2379-18 provides two power supply pins: the 2.5v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2379-18 to communicate with any digital logic operating between 1.8v and 5v, including 2.5v and 3.3v systems. power supply sequencing the ltc2379-18 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2379 -18 has a power-on-reset (por) circuit that will reset the ltc2379-18 at initial power-up or whenever the power supply voltage drops below 1v. once the supply voltage re-enters the nominal supply voltage range, the por will
ltc2379-18 15 237918f reinitialize the adc. no conversions should be initiated until 20s after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control cnv timing the ltc2379-18 conversion is controlled by cnv. a ris - ing edge on cnv will start a conversion and power up the ltc2379-18. once a conversion has been initiated, it cannot be restarted until the conversion is complete. for optimum performance, cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40ns from the start of the conversion or after the conversion has been completed. once the conversion has completed, the ltc2379-18 powers down and begins acquiring the input signal. internal conversion clock the ltc2379-18 has an internal clock that is trimmed to achieve a maximum conversion time of 412ns. with a min- imum acquisition time of 200ns, throughput performance of 1.6msps is guaranteed without any external adjustments. auto power-down the ltc2379-18 automatically powers down after a con - version has been completed and powers up once a new conversion is initiated on the rising edge of cnv. during power down, data from the last conversion can be clocked out. to minimize power dissipation during power down, disable sdo and turn off sck. the auto power-down feature will reduce the power dissipation of the ltc2379-18 as the sampling frequency is reduced. since power is con - sumed only during a conversion, the ltc2379-18 remains applications information powered-down for a larger fraction of the conversion cycle (t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 12. digital interface the ltc2379-18 has a serial digital interface. the flexible ov dd supply allows the ltc2379-18 to communicate with any digital logic operating between 1.8v and 5v, including 2.5v and 3.3v systems. the serial output data is clocked out on the sdo pin when an external clock is applied to the sck pin if sdo is enabled. clocking out the data after the conversion will yield the best performance. with a shift clock frequency of at least 100mhz, a 1.6msps throughput is still achieved. the serial output data changes state on the rising edge of sck and can be captured on the falling edge or next rising edge of sck. d17 remains valid till the first rising edge of sck. the serial interface on the ltc2379-18 is simple and straightforward to use. the following sections describe the operation of the ltc2379-18. several modes are provided depending on whether a single or multiple adcs share the spi bus or are daisychained. sampling rate (khz) 0 200 400 600 800 1600 1400 1200 1000 0 power supply current (ma) 5 4 2 1 3 8 7 6 237918 f12 i vdd i ref i ovdd figure 12. power supply current of the ltc2379-18 versus sampling rate
ltc2379-18 16 237918f timing diagram normal mode, single device when chain = 0, the ltc2379-18 operates in normal mode. in normal mode, rdl/sdi enables or disables the serial data output pin sdo. if rdl/sdi is high, sdo is in high-impedance. if rdl/sdi is low, sdo is driven. figure 13 shows a single ltc2379-18 operated in normal mode with chain and rdl/sdi tied to ground. with rdl/ sdi grounded, sdo is enabled and the msb(d17) of the new conversion data is available at the falling edge of busy. this is the simplest way to operate the ltc2379-18. cnv ltc2379-18 busy convert irq data in digital host clk sdo sck 238018 f13a rdl/sdi chain 237918 f13 convert convert t acq t acq = t cyc ? t conv ? t busylh power-down and acquire power-down and acquire cnv chain = 0 busy sck sdo rdl/sdi = 0 t busylh t dsdobusyl t sck t hsdo t sckh t quiet t sckl t dsdo t conv t cnvh t cyc t cnvl d17 d16 d15 d1 d0 1 2 3 16 17 18 figure 13. using a single ltc2379-18 in normal mode
ltc2379-18 17 237918f timing diagram normal mode, multiple devices figure 14 shows multiple ltc2379-18 devices operating in normal mode(chain = 0) sharing cnv, sck and sdo. by sharing cnv, sck and sdo, the number of required signals to operate multiple adcs in parallel is reduced. since sdo is shared, the rdl/sdi input of each adc must be used to allow only one ltc2379-18 to drive sdo at a time in order to avoid bus conflicts. as shown in figure 14, the rdl/sdi inputs idle high and are individually brought low to read data out of each device between conversions. when rdl/sdi is brought low, the msb of the selected device is output onto sdo. 237918 f15 rdl b rdl a convert irq data in digital host clk cnv ltc2379-18 sdo a sck rdl/sdi cnv ltc2379-18 sdo b sck rdl/sdi chain busy chain 237918 f14 d17 a sdo sck cnv busy chain = 0 rdl/sdi b rdl/sdi a d17 b d16 b d1 b d0 b d15 b d16 a d15 a d1 a d0 a hi-z hi-z hi-z t en t hsdo t dsdo t dis t sckl t sckh t cnvl 1 2 3 16 17 18 19 20 21 34 35 36 t sck convert convert t quiet t conv t busylh power-down and acquire power-down and acquire figure 14. normal mode with multiple devices sharing cnv, sck and sdo
ltc2379-18 18 237918f timing diagram ov dd 237918 f15a convert irq data in digital host clk cnv ltc2379-18 busy sdo b sck rdl/sdi cnv ltc2379-18 sdo a sck rdl/sdi chain ov dd chain when chain = ov dd , the ltc2379-18 operates in chain mode. in chain mode, sdo is always enabled and rdl/sdi serves as the serial data input pin (sdi) where daisychain data output from another adc can be input. this is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. figure 15 shows an example with two daisychained devices. the msb of converter a will appear at sdo of converter b after 18 sck cycles. the msb of converter a is clocked in at the sdi/rdl pin of converter b on the rising edge of the first sck. 237918 f15 d0 a d1 a d16 a d17 a d15 b d16 b d17 b sdo b sdo a = rdl/sdi b rdl/sdi a = 0 d0 b d1 b d15 a d16 a d17 a d0 a d1 a 1 2 3 16 17 18 19 20 34 35 36 t dsdobusyl t ssdisck t hsdisck t busylh t conv t hsdo t dsdo t sckl t sckh t sckch t cnvl t cyc convert convert sck cnv busy chain = ov dd t quiet power-down and acquire power-down and acquire figure 15. chain mode timing diagram
ltc2379-18 19 237918f board layout to obtain the best performance from the ltc2379-18 a printed circuit board is recommended. layout for the printed circuit board (pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layout the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1783a, the evaluation kit for the ltc2379-18. partial top silkscreen
ltc2379-18 20 237918f board layout partial layer 1 component side partial layer 2 ground plane
ltc2379-18 21 237918f board layout partial layer 3 pwr plane partial layer 4 bottom layer
ltc2379-18 22 237918f u6 nc7sz66p5x c13 0.1f 4 1 2 9 cnv sck c20 47f 6.3v 0805 c56 0.1f cnv ref gnd gnd gnd gnd ref/dgc v dd v ref 0.8v ref ov dd sck sdo busy rdl/sdi sdo busy rd ltc2379-18 in ? in + 5 4 13 14 11 12 b a 5 3 gnd v cc oe +3.3v r5 49.9 1206 r6 1k u8 nc7sz04p5x u2 nc7svu04p5x u20 ltc6655ahms8-5 u3 nl17sz74 u4 nc7svu04p5x cnvst_33 from cpld clk to cpld c5 0.1f c1 0.1f c11 0.1f shdn gnd gnd out_f gnd gnd 9v to 10v 1 2 3 4 8 7 6 5 +3.3v +3.3v +3.3v 3 4 2 5 3 4 2 5 c2 0.1f r3 33 r2 1k r1 33 +3.3v +3.3v 3 1 4 6 2 8 7 5 r8 33 c3 0.1f r4 33 c4 0.1f v in out_s gnd v cc clr\ q\ cp q d pr\ 3 4 2 5 +3.3v dc590 detect to cpld +3.3v c58 opt u9 nc7sz04p5x c15 0.1f c16 0.1f 3 4 2 5 +3.3v r13 1k r17 2k r10 4.99k u7 24lc025-i/st r11 4.99k r12 4.99k c14 0.1f 6 8 4 237918 bl 5 7 3 2 1 scl sda array eeprom wp a2 a1 a0 v ss v cc 1 3 5 7 9 11 13 2 4 6 8 10 12 14 j3 dc590 sdo sck cnv 9v to 10v r7 1k 10 16 6 3 1 15 7 2 8 jp6 fs 1 2 3 hd1x3-100 opt c7 0.1f c6 10f 6.3v +2.5v c10 0.1f c39 3300pf npo c19 3300pf 1206 npo r38 opt r36 20 r35 opt r45 ? r34 0 c40 3300pf npo c9 10f 6.3v r16 0 r32 20 out1 v + v ? v+ shdn out2 5 4 ?in1 +in1 8 7 3 +in2 2 6 r19 0 + ? r18 1k r31 opt u15 lt6350cms8 r32 0 c42 15pf c45 10f c55 1f v + v ? c57 0.1f r37 opt r9 opt c61 10f 6.3v c63 10f 6.3v c62 1f c43 0.1f r15 opt c18 opt c17 10f jp2 cm e7 ext_cm 1 +2.5v 2 3 v ref/2 ext hd1x3-100 c8 1f c46 1f r40 1k r39 0 1 2 3 coupling ac dc jp1 hd1x3-100 c44 1f c49 opt c48 10f 6.3v c47 opt r41 opt c59 1f c60 0.1f 1 2 3 jp5 hd1x3-100 coupling ac dc db16 db17 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 clkout 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 j2 con-edge 40-100 clk in j1 j4 j8 r14 0 a in + a in ? ? + board layout partial schematic of demoboard
ltc2379-18 23 237918f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de16) dfn 0806 rev ? pin 1 notch r = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006)
ltc2379-18 24 237918f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0311 ? printed in usa lt6350 3.01k 4.32k v cm 237918 ta03 out1 r int r int r in = 15k out2 v ? 8 4 5 2 1 6 v + 3 + ? ? + 20 3300pf 20 6.04k 1k v cm 1k 0.5v 4.5v 0.5v 4.5v 5v 5.5v 47f 10f 10f ltc2379-18 ref/dgc in + ref v dd 2.5v in ? ?10v 10v 0v 3300pf 3300pf 5.5v ltc6655-5 v in v out_s v out_f related parts typical application lt6350 configured to accept a 10v input signal while running off of a single 5.5v supply when digital gain compression is enabled in the ltc2379-18 part number description comments adcs ltc2383-16/ltc2382-16/ ltc2381-16 16-bit, 1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 92db snr, 2.5v input range, pin compatible family in msop-16 and 4mm w 3mm dfn-16 package ltc2393-16/ltc2392-16/ ltc2391-16 16-bit, 1msps/500ksps/250ksps parallel/serial adc 5v supply, differential input, 94db snr, 4.096v input range, pin compatible family in 7mm w 7mm lqfp-48 and qfn package ltc1864/ltc1864l 16-bit, 250ksps/150ksps 1-channel power, adc 5v/3v supply, 1-channel, 4.3mw/1.3mw, msop-8 package ltc1865/ltc1865l 16-bit, 250ksps/150ksps 2-channel power adc 5v/3v supply, 1-channel, 4.3mw/1.3mw, msop-8 package ltc2302/ltc2306 12-bit, 500ksps, 1-/2-channel, low noise, adc 5v supply, 14mw at 500ksps, dfn-10 package ltc2355-14/ltc2356-14 14-bit, 3.5msps serial adc 3.3v supply, 1-channel, unipolar/bipolar, 18mw, msop-10 package dacs ltc2757 18-bit, single parallel i out softspan? dac 1lsb inl/dnl, software-selectable ranges, 7mm w 7mm lqfp- 48 package ltc2641 16-bit single serial v out dacs 1lsb inl, 1lsb dnl, msop-8 package, 0v to 5v output ltc2630 12-bit/10-bit/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12bits) references ltc6655 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt6350 low noise single-ended-to-differential adc driver rail-to-rail input and outputs, 240ns 0.01% settling time lt6200/lt6200-5/ lt6200-10 165mhz/800mhz/1.6ghz op amp with unity gain/av = 5/av = 10 low noise voltage: 0.95nv/ hz (100khz), low distortion: C80db at 1mhz, tsot23-6 package lt6202/lt6203 single/dual 100mhz rail-to-rail input/output noise low power amplifiers 1.9nv hz , 3ma maximum, 100mhz gain bandwidth ltc1992 low power, fully differential input/output amplifier/ driver family 1ma supply current

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